1. Field of the Invention
This invention is related to the field of clocking of integrated circuits and, more particularly, to multiplying the frequency of a clock.
2. Description of the Related Art
Integrated circuits may include clock multiplier circuits. Generally, the clock multiplier circuit in an integrated circuit is used for multiplying the frequency of a clock input (or inputs) to the integrated circuit to generate one or more clocks for internal use within the integrated circuit. The clock multiplier may be used to allow lower frequency clocks to be supplied to the integrated circuit, while still allowing the higher frequency operation within the integrated circuit.
One typical method for building a clock multiplier circuit is using a phase-locked loop (PLL). Generally, a PLL requires a certain amount of time (lock time) to adapt if the input clock frequency is changed during operation or if the multiplier ratio (between the output of the clock multiplier circuit and the input clock signal) is changed during operation. Similarly, if the clock input is stopped, the PLL may require a certain amount of time to stop. If the input clock is restarted, the PLL may require the lock time to restart in a predictable fashion. While a maximum lock time may be specified, the actual lock time may not be predetermined. Variations in lock time may occur due to process parameters in the fabrication process, operating temperature, supply voltage, etc.
In some cases, the lack of determinism in the operation of the PLL may be problematic. For example, during testing of the integrated circuit, determinism in the clocking may be desired in order to generate test results that may be matched with expected results. If the number of clock periods that have elapsed in the integrated circuit is not deterministic, it may be difficult to observe state in the integrated circuit and verify that the state is correct as expected by the test.
In one embodiment, an integrated circuit includes a clock multiplier circuit and a core configured to be clocked by an output clock signal of the clock multiplier circuit. The clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable.
In another embodiment, a clock multiplier circuit is coupled to supply an output clock signal, and includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The width of each of the pulses is independent of a frequency of the signal and is independent of the number of pulses. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.